A semiconductor storage apparatus, such as a mask ROM, is known as an information storage apparatus. This mask ROM is of such a ROM as to write information to memory cell transistors in a mask process, that is, fix "1" or "0" information, this being a so-called read-only memory.
FIG. 1 is a circuit diagram showing part of a conventional mask ROM which is structured with the use of MOS type memory cell transistors. In FIG. 1, Q1 to Q8 show MOS type memory transistors and the transistors Q1 to Q8 are connected at their gate electrodes to word lines WL1 to WL8. The transistors Q1 to Q8 are connected at their drain electrodes commonly to a bit line BL1 and grounded at their source electrodes. Depending upon whether the MOS type transistor is of an enhancement type or a depletion type ion implanted to vary the threshold value, their fixed storage contents are made to correspond to "1" and "0". In such a structure, the transistor Q1 is made fixed to "0" and the transistor Q2 to "1", for example.
In the mask ROM thus formed, when 8-bit information or one-word information for instance is to be read out, dedicated word lines are required for the respective bits and it is, therefore, necessary to provide eight word lines in total. If, here, it is only necessary to use one word line so as to read out one-word information, then the mask ROM structure can be very much simplified.
In order to read out the one-word information of a multi-bit configuration in the conventional mask ROM it will be necessary to use word lines corresponding to the number of bits. In consequence, the mask ROM becomes complicated in configuration and it has been impossible to reduce the area of memory cells by that extent.
Although only one bit information can be recorded or reproduced with a conventional memory cell, such as one transistor, if it is possible to record and reproduce plural-bit information or multi-valued information with one memory cell, then the mask ROM can be made in highly compact form.